1. Field of the Invention
The invention relates to a frequency synthesizer, and more particularly, to a fractional frequency synthesizer.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a block diagram of a conventional phase-locked loop (PLL) 100. The PLL 100 is used for generating a frequency signal Sf1 according to an input signal Sin1. As shown in FIG. 1, the PLL 100 includes a phase detector (PD) 110, a loop filter 120, a voltage-controlled oscillator (VCO) 130, and a frequency divider 140. However, there is a dilemma when considering the practical circuit design of the conventional PLL 100. Suppose that the input signal Sin1 is a low-frequency signal and the frequency signal Sf1 is a high-frequency signal. When considering the input signal Sin1, the loop bandwidth of the PLL 100 should be designed to be narrow enough to filter out the jitter of the input signal Sin1; however, when considering the frequency signal Sf1 from the VCO 130, the loop bandwidth of the PLL 100 should be wide enough to eliminate the jitter of the frequency signal Sf1 due to the VCO. In a general implementation, the frequency ratio of the frequency signal Sf1 to the input signal Siin1 of the conventional PLL 100 differs roughly by a factor of tens. In a liquid crystal display (LCD) controller circuit, however, the input signal Sin1 is a reference signal (i.e., a horizontal synchronization signal, HSYNC). In this case, the frequency of the reference signal can be tens of KHz (e.g. 30˜100 KHz), but the frequency of the frequency signal Sf1 can be up to hundreds of MHz (e.g. 25˜200 MHz). Therefore, the frequency ratio of the frequency signal Sf1 to the input signal Sin1 differs roughly by a factor of thousands. In this situation, the PLL 100 will fail to effectively eliminate the jitter of the frequency signal Sf1 due to the VCO and the input signal Sin1 at the same time.
U.S. Pat. No. 6,686,784 discloses a hybrid phase-locked loop to solve the above-mentioned problem. To effectively eliminate jitter of both the frequency and the input signal, however, the prior art hybrid phase-locked loop is composed of two analog phase-locked loops and one phase selector, resulting in increased manufacturing cost and higher circuit complexity.